- imperative programming, as opposed to functional or declarative programming
- destined for sequential execution rather simultaneous / parallel execution
- manipulating discrete data (discrete signals) rather emulating continuous data (analog signals)
- respecting best effort execution time constraints instead of real time execution constraints (is this the same as sequential vs. parallel ? not quite : here it's about how software deals with inputs and the notion of time; there it was about how the resources are alloted to each task)
But one day the optics teacher said: "In order to become an optical networks engineer nowadays, there are a sum of skills to posess : a pinch communications theory, a drop of digital electronics, a whiff of programming".
I took a course in digital electronics, where I learned about hardware description languages, in particular Verilog and VHDL. The 'synchronous processes' paradigm that is characteristic to hardware was so much more appealing to me than old fashionned 'shoot and reload' approach of all interpreters, compilers and the like.
Later I went on to discover VHDL-AMS and the description of continuous-time, continuous-data systems. AMS stands for Analog and Mixed Signal. The world in which we live - sounds, light intensities, temperatures, concentrations, efforts, translations - are all analog signals, so suddenly software was no longer restrained to a 0 and 1 abstract space; it was so much closer to how I knew, felt and experienced the world due to my physics-oriented training.
Now back to Esterel ! Far as I have understood, it's meant to be a description language, just like VHDL, but on a higher abstraction level. It features a much facilitated description of parallelism. However Esterel is not just about specifying RTL netlists; it is meant to describe all possible finite state machines (FSM, automata), wether their implementation is to be written in software or in hardware.
"Esterel compiler[...]translates programs into C for simulation or software implementation and into Verilog or VHDL RTL-logic for hardware synthesis."
The designer can then chose which part of the automata is implemented software and which in hardware :
"One can use Esterel to first implement or simulate a system entirely in software, validate it, and then automatically turn it to hardware. Such a flow has many desirable properties, including the ability to keep a single specification for hardware and software while formally guaranteeing the same behavioral properties of the design. Furthermore, one has a lot of flexibility to partition the system description so that some of it is realized in hardware and the rest is mapped to software."
(from 'System Level Design and Verification Using a Synchronous Language', G. Berry, M. Kishinevsky, S. Singh)
In fact the role of Esterel is similar to other high level system description languages, such as SystemC and System Verilog. And its specificity with regard to those languages lies with its being a 'formally defined' language, which facilitates the formal verification of the described automata. I.E. ensuring that the computer behaves as expected, under all circumstances.
As to Lustre - it is also a synchronous programming language, but unlike Esterel - which is imperative, Lustre is a declarative language. Since it's been developped by the same company, I guess it is safe to assume that it is complementary in purpouse to Esterel.
For more insight into these languages, some in depth reading and coding practice is probably required.
